Semiconductor device usually includes multiple metal layers to provide sufficient interconnection. The interconnection between the multiple metal layers and the connection between active region of the semiconductor device and external circuit can be achieved by filling through holes with conductive materials.
With the development of ultra-large-scale integration, the number of layers of the metal layers in the semiconductor device increases. As feature dimensions of ICs reduce, the size of the through hole gradually decreases. The smaller the size of the through hole, the more difficult to form the through hole. The formation quality of the through hole greatly affects the performance of the back end of line (BEOL) circuit, and could even affect the normal operation of the semiconductor device.
However, conventionally formed through hole may easily cause degradation of the electrical performance of the semiconductor device. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.